Extrinsic semiconductors rely on dopants to provide a desired density of charge carriers. Two major steps are involved: dopant implantation and dopant activation. In conventional CMOS manufacturing, an ion beam implants dopants into the wafer, but they are not yet in position to provide the desired charge carrier density. Dopants can only contribute carriers when they are activated, or placed at silicon sites in the crystal lattice. After implantation, a high temperature anneal step has traditionally been used to activate the dopant ions and correct the lattice damage caused by the implant. If a soak anneal process is used, activation temperatures may exceed 1000° C.
Rapid Thermal Processing (RTP) spike annealing has been used as an alternative to bulk silicon thermal soak annealing for dopant activation. RTP spike annealing offers rapid surface anneal (second level) at a high temperature (>1000° C.) to maximize electrical activation of dopants with less diffusion.
However, traditional RTP spike anneal with specified thermal radiation wavelength suffered from a pattern loading effect due to differences in thermal absorption for different materials. Wafers having a variety of surface materials with different reflectances do not heat evenly. Regions having a low reflectance heat up less than regions having a high reflectance, interfering with uniformity of the dopant activation in the doped areas.
Improved dopant activation methods are desired.